Date: April 24, 2018 at 1:00 pm ET
Free to attend
Length: Approximately one hour
Since 2006, abounding of new 3D NAND Flash beef accept been proposed and commercialized on the market. Already, we accept apparent 3D NAND corpuscle anatomy up to 64L/72L with distinct or multi-stack NAND cord architecture. The anamnesis body on Micron/Intel’s 64L 3D NAND 256 Gb/die accomplished 4.40 Gb/mm2 (256 Gb/die). In this session, we’ll overview 3D NAND Flash roadmap, products, corpuscle design, structure, abstracts and action integration. The 3D NAND corpuscle architectonics from above NAND manufacturers including Samsung TCAT V-NAND, Toshiba/Western Digital BiCS, SK Hynix P-BiCS and Micron/Intel FG CuA will be advised and compared. Current and approaching technology challenges on 3D NAND will be discussed as well.
Dr. Jeongdong Choe, Senior Technical Fellow, TechInsights
Jeongdong Choe is a Senior Technical Fellow for TechInsights. He has a Ph.D. in cyberbanking engineering and over 26 years’ acquaintance including 100 filed/issued patents in semiconductor action affiliation for DRAM, (V) NAND, SRAM and argumentation devices. Prior to abutting TechInsights in 2011, he formed as a Team Lead in R&D for SK-Hynix and Samsung area he optimized action and accessory architectures with avant-garde technologies for accumulation production. Jeongdong has been a affiliate of the ‘Future Technology Roadmap’ and ‘Patent Examination’ committees at Samsung, and has led a Action Consulting Group for advanced/emerging NVM accessories such as STT-MRAM, ReRAM, and PCRAM and SOI/FinFET/HKMG accessory for 2x/1x nm approaching argumentation and anamnesis devices. He has additionally accounting abounding accessories including DRAM Makers Turn to New Action for Sub 2x/1x nm Cells, and Comparing Leading-Edge 2x/1x nm NAND Flash Memories. Jeongdong annually produces a broadly broadcast roadmaps for Anamnesis Technology. At Samsung, as Team Lead of NAND FLASH Action Architecture, he avant-garde next-generation devices, including 42 nm, 35 nm, 27 nm, 21 nm and 19 nm action nodes with optimized DPT (double apery technology) for 3x and 2x accessories and TPT (triple apery technology) for 1x devices, as able-bodied as for sub-20 nm terabit bearing for 3D-NAND, including TCAT and VG-NAND architecture.
Sponsored by Tech Insights:
For over 25 years TechInsights has been a trusted apparent and technology accomplice to the world’s better and best acknowledged companies including 37 of the top 50 U.S. apparent holders. By absolute the addition others can’t central the broadest ambit of avant-garde technology products, we prove apparent amount and accredit business leaders to accomplish the best, fact-based IP and technology advance decisions.
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